description the AMS3400SRG is the nchannel logic enhancement mode power field effect transistor is produced using high cell density, dmos trench te chnology. this highdensity process is especially tailored to minimize onstate resistance. these devices are particularly suited for low voltage app lication such as cellular phone and notebook computer power management and other batter y powered circuits where high side switching . pin configuration sot-23 1.gate 2.source 3.drain part marking sot-23 y: year code a: week code feature 30v/5.8a, r ds(on) = 25m (typ.) @v gs = 10v 30v/4.8a, r ds(on) = 30m @v gs = 4.5v 30v/4.0a, r ds(on) = 40m @v gs = 2.5v super high density cell design for extremely low r ds(on) exceptional onresistance and maximum dc current capability sot23 package design 3 1 2 d g s 3 1 2 a0ya
! ! electrical characteristics ( ta = 25 n unless otherwise noted ) parameter symbol condition min typ max unit static drainsource breakdown voltage v (br)dss v gs =0v,i d =250ua 30 v gate threshold voltage v gs(th) v ds =vgs,i d =250ua 0.5 1.5 v gate leakage current i gss v ds =0v,v gs = 12v 100 na zero gate voltage drain current i dss v ds =24v,v gs =0v 1 ua v ds =24v,v gs =0v t j =55 n 10 drainsource onresistance r ds(on) v gs =10v,i d =5.8a v gs =4.5v,i d =4.8a v gs =2.5v,i d =4.0a 25 30 40 m nr forward transconductance g fs v ds =4.5v,i d =5.8a 12 s diode forward voltage v sd i s =1.7a,v gs =0v 1.2 v dynamic total gate charge q g v ds =15v v gs =10v i d n 6.7a 9.7 18 nc gatesource charge q gs 1.6 gatedrain charge q gd 3.1 input capacitance c iss v ds =15v v gs =0v f=1mh z 450 pf output capacitance c oss 240 reverse transfer capacitance c rss 38 turnon time t d(on) tr v dd =15v r l =15 nr i d =1.0a v gen =10v r g =6 nr 7 15 ns 10 20 turnoff time t d(off) tf 20 40 11 20
! ! sot-23 package outline o !
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